Poly-phase local oscillator

ABSTRACT

One embodiment of the present invention features a poly-phase local oscillator generator combining frequency dividers and direct-injection-locked phase correctors. The poly-phase local oscillator generator comprises a plurality of phase correctors configured to relax frequency and tuning range of a reference local oscillator (LO), and a plurality of frequency dividers, coupled to the phase correctors, configured to offer different frequency segments. The phase correctors are expandable, so that phase accuracy can be optimized by cascading more of themselves.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present generally relates to a poly-phase local oscillator, moreparticularly, to a poly-phase local oscillator generator combiningfrequency dividers and expandable phase correctors.

2. Description of the Related Art

Improvements of sharing the geographically unused white spaces in TVband (54 to 864 MHz) has led to the development of IEEE 802.22 wirelessregional area network (WRAN) [1], which embodies the cognitive radio(CR) techniques to enable an opportunistic share of the spectrum [2]. Toavoid causing detrimental interference to the incumbent primary users,one key challenge of such a TV-band transmitter (TX) lies on managingthe unwanted harmonic emission [3] without pricy or complicatedfiltering modules [4].

Harmonic rejection mixers (HRMs), which are designed to reject localoscillator (LO) harmonics (or “images”), permits a saving on radiofrequency (RF) band-filtering to be made, for example insoftware-defined radio (SDR). Usual implementations of HR mixers use aweighted combination of hard-switching mixers that need carefulalignment of phase and gain parameters. Hard-switching mixer is one ofthe sources generating influential sidebands associated with theharmonics of the local oscillator (LO). Multi-path mixers feature thedesired integratability and wideband ability in harmonic rejection [5].A typical differential mixer already can stem all even harmonics, whilerejecting the odd ones entails additional paths. The 6-pathharmonic-reject mixer (6P-HRM) [6] can suppress the critical 3^(rd) and5^(th) harmonics by around 35 dB under typical 1% gain and 1° phaseerrors, but it is still not the whole for a TX covering a 16x-wide RFrange, i.e., harmonics up to the 15^(th) are in-band. An activetunable-LC filter [7] can be employed to extend both harmonic rejectionratio (HRR) (42 dB) and the number of rejecting harmonics (up to15^(th)), but the power (171 mW) is penalized to uphold the linearity,while calibration should be adopted to surmount the LC-tank variation.Although the 18-path HRM (18P-HRM) is capable to reject harmonics up tothe 15^(th) (40 dB HRR) and suppress certain distortion sidebands, theenforced baseband (BB) input (18 paths, 18 phases) and LO format (18phases, 33% duty cycle) are complicated. The former implies 7 moredifferential digital-to-analog converters and 14 more I/O pins than the6P-HRM. The latter resorted from a div-by-9 ring counter drawssubstantial power (156 mW) and entails a high-frequency reference LO(LO_(ref)=9xRF), adding complexity to the frequency synthesis.

In fact, the constraint of high LO_(ref) is shared by most HRM-basedarchitectures. For the receiver in [9], LO_(ref)=8xRF is entailed forprecise 8-phase LO generation, limiting its operating bandwidth (BW)between 400 to 900 MHz (albeit a 5 GHz signal-path BW). Another exampleis [10], the rotational 16P-HRM entails LO_(ref)=16xRF, restricting itsoperating BW between 100 to 300 MHz while drawing considerable power(69.8 mW at 100 MHz).

In order to break the common constraint of high-frequency reference LO(LO_(ref)) in existing HRM-based architecture [7]-[10], this inventiondescribes a number of techniques to realize a wideband TX with high HRRachieved on chip, measuring more favorable power (53 to 75 mW) and HRR(59.3 dB) than the prior art [7], [8].

SUMMARY OF THE INVENTION

According to the present invention there is provided a poly-phase localoscillator generator, comprising: a plurality of phase correctorsconfigured to relax frequency and tuning range of a reference localoscillator (LO); and a plurality of frequency dividers, coupled to thephase correctors, configured to offer different frequency segments;wherein the plurality of phase correctors are expandable by cascadingmore of themselves for enhancing phase-correcting ability.

Further, the plurality of phase correctors are direct-injection-lockedphase correctors. The plurality of frequency dividers areeven-ratio-only frequency dividers.

The poly-phase local oscillator generator disclosed herein may beimplemented in any means for achieving various aspects, and otherfeatures will be apparent from the accompanying drawings and from thedetailed description that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The various embodiments of the present invention are illustrated by wayof example, and not by way of limitation, in the figures of theaccompanying drawings and in which:

FIG. 1 (a) illustrates architecture of a proposed transmitter accordingto an embodiment of the present invention

FIG. 1 (b) shows system plan for the lower sub-band (54 to 432 MHz)

FIG. 1 (c) shows system plan for the upper sub-band (432 to 864 MHz).

FIG. 2 (a) illustrates one example of single-ended diagram ofsingle-stage 6P-HRM.

FIG. 2 (b) illustrates one example of single-ended diagram ofsingle-stage 14P-HRM.

FIG. 3 (a) illustrates one example of single-ended diagram of two-stage6P-HRM.

FIG. 3 (b) illustrates one example of single-ended diagram of two-stage14P-HRM.

FIG. 4 shows harmonic rejection ratio (HRR) of 6P-HRM and 14P-HRM underfour combinations of gain and phase mismatches.

FIG. 5 (a) illustrates one example of vector diagram for gain mismatchillustration of the two-stage 6P-HRM.

FIG. 5 (b) illustrates one example of two-stage approximated gain ratioof the 1^(st) harmonic.

FIG. 6 (a) illustrates one example of vector diagram for gain mismatchillustration of the two-stage 14P-HRM.

FIG. 6 (b) illustrates one example of two-stage approximated gain ratioof the 1st harmonic.

FIG. 7 shows theoretical HRR₃ of 6P-HRM (upper) and 14P-HRM (lower)versus 3σ_(φ).

FIG. 8 (a) illustrates one embodiment of detailed schematic of theproposed transmitter.

FIG. 8 (b) illustrates one example of circuit diagram of lowpass filterin FIG. 8 (a)

FIG. 8 (c) illustrates one example of circuit diagram of mixer bank inFIG. 8 (a)

FIG. 8 (d) illustrates one example of circuit diagram ofharmonic-rejection filter in FIG. 8 (a)

FIG. 9 (a) illustrates one embodiment of driver amplifier with embeddedband-selection filter.

FIG. 9 (b) illustrates a diagram showing simulated magnitude responsesof the driver amplifier with and without BSF and R_(d)C_(d)degeneration.

FIG. 10 (a) shows 4-phase LO generation using cascaded DIL 4PC.

FIG. 10 (b) shows 8-phase LO generation using cascaded DIL 8PC.

FIG. 11 illustrates one embodiment of proposed 8-116-phase LOG and itscircuit details.

DESCRIPTION OF THE EMBODIMENTS

Various exemplary embodiments, features, and aspects of the inventionwill be described in detail below with reference to the drawings. Theinvention is to be understood that each specific element includes alltechnical equivalents that operate in a similar manner to accomplish asimilar purpose. Various terms that are used in this specification areto be given their broadest reasonable interpretation when used ininterpreting the claims.

Moreover, features and procedures whose implementations are well knownto those skilled in the art are omitted for brevity. For example,design, selection, and implementation of basic electronic circuitelements such as bias elements, current mirror arrangements, logicelements, current and voltage sources, metal oxide semiconductor fieldeffect transistors (MOSFETs), and the like, lie within the ability ofthose skilled in the art, and accordingly any detailed discussionthereof may be omitted.

Referring firstly to FIG. 1( a) there is shown schematically theproposed wideband direct-upconversion TX architecture aiming at a 60 dBHRR for all LO harmonics. The TV band is partitioned into lower (54 to432 MHz) and upper (432 to 864 MHz) sub-bands.

The lower sub-band is handled by a scheme: Two-Stage 14P-HRM+PassiveFiltering. Unlike the single-stage HRMs [6]-[8], the two-stage FIRMexpanded from [9] is highly robust to the gain error by making it theproduct of stage errors (details in Sub-Section III-D). Comparing withthe 18P-FIRM, the 14P-HRM rejects one less harmonic (i.e., the 15^(th)),but the requested BB inputs (4 paths, 4 phases) and LO format (16phases, 50% duty cycle) are much simpler. As shown in FIG. 1( b), theworst HRR happens at the lowest RF of 54 MHz. The far-out 15^(th)harmonic at 810 MHz has an inherent attenuation of 23.5 dB, and can beeasily furthered by filtering. Unlike the active LC-notch filter [7],here a simple 2^(nd)-order passive-RC lowpass filter (LPF) is employedas the harmonic-rejection filter (HRF), having neither power norlinearity overhead. A few BW steps automatically selected with the LObands are simple enough to enhance both in-band and out-band HRRs.

For the upper sub-band, it is handled by a scheme: Two-Stage6P-HRM+Passive Filtering. As shown in FIG. 1( c), the worst HRR occursat 432 MHz RF, locating the first uncancelled 7^(th) harmonic at around3 GHz which is far from the TX BW, and will be well-suppressed by theHRF.

In order to band-limit the output noise spectrum and further theout-band HRR, the driver amplifier (DA) features another 3^(rd)-orderpassive-CLC LPF to serve as a band-selection filter (BSF). Both the BSFand HRF are low Q and thereby immune to process variations.

Counting all filtering, and the intrinsic decay of LO-harmonic power,the HRR requested from the two-stage 6P-HRM (14P-HRM) is relaxed to 36dB (43 dB) for the 60 dB HRR target. This relaxation implies lowerLO-phase-error requirement from the 8-/16-phase LO generator (LOG),given that the gain error has been made insignificant to the HRR underthe two-stage HRMs. The principles of single-/two-stage 6P-HRM and14P-HRM are presented next.

Single-Stage 6P-HRM and 14P-HRM

FIG. 2( a) depicts the single-ended diagram of single-stage 6P-HRM. Itentails an 8-phase LOG for 45° phase shifting and a gain ratio[cos(π/4):1:cos(π/4)] between paths. The limitation of 6P-HRM is thatmainly the 3^(rd), 5^(th), 11^(th) and 13^(th) harmonics are rejected.Alternatively, the single-stage 14P-HRM [FIG. 2( b)] rejects harmonicsup to the 13^(th). It entails a 16-phase LO for 22.5° phase shifting,and a gain ratio[cos(3π/8):cos(π/4):cos(π/8):1:cos(π/8):cos(π/4):cos(3π/8)] betweenpaths, which can be numerically approximated as[1:1.8478:2.4142:2.6131:2.4142:1.8478:1].

Two-Stage 6P-HRM and 14P-HRM for TX

Both two-stage 6P-HRM [FIG. 3( a)] and 14P-HRM [FIG. 3( b)] involve gainweighting at BB and RF, phase rotation and signal recombination. Toresolve the gain mismatch, the selected gain ratios should be obtainedvia minimizing the cost function between the true and approximatedvalues, while easing the circuit implementation.

For the two-stage 6P-HRM, the irrational gain ratio[cos(π/4):1:cos(π/4)] is realized half at BB with a pre-gain ratio[2/5:3/5:2/5], and half at RF with a post-gain ratio [4:5.6:4]. The 45°phase rotation is embodied into the mixers driven by an 8-phase LO.After all, the resultant gain ratio is [29:41:29]. This approximationhas <0.1% relative error when compared to their true values. To bedescribed later, such pre-gain ratio befits circuit realization in theBB LPFs, whereas the post-gain ratio minimizes the switching elementsbetween 6P-HRM and 14P-HRM.

Similarly, for the 14P-HRM, its irrational gain ratio[cos(3π/8):cos(π/4):cos(π/8):1:cos(π/8):cos(π/4):cos(3π/8)] is realizedhalf at BB with a pre-gain ratio [1/5:1/2:5/8:3/5:5/8:1/2:1/5] and halfat RF with a post-gain ratio [4:3:4]. The mixers driven by a 16-phase LOrealize the 22.5° phase rotation. The resultant gain ratio[1:1.8462:2.4134:2.6154:2.4134:1.8462:1] has <0.1% relative error whencompared to their true values.

Gain and Phase Mismatches of 6P-HRM and 14P-HRM

The intrinsic HRR of 6P-HRM and 14P-HRM can be compared in terms ofrandom gain and phase mismatches. The concerned HRR expressions aresummarized in TABLE I. σ_(A) and σ_(φ) are the standard deviations ofthe gain and phase mismatches, respectively. Note that the HRR has nodifference between single-stage and two-stage HRMs. The only differenceis on σ_(A) [9]. Several HRR cases under different combinations of σ_(A)and σ_(φ) are plotted in FIG. 3. The square-wave-like LO is based on aduty cycle (d) of 50% for generality. As expected, the 14P-HRM rejectssignificantly more the 7^(th) and 9^(th) harmonics, and is inherentlymore robust to gain mismatch. The next sub-section describes theeffectiveness of two-stage 6P-HRM and 14P-HRM in gain mismatchreduction.

TABLE I Inherent HRR of 6P-HRM and 14P-HRM. 6P-HRM * 14P-HRM * HRR₃$- {\frac{\sin^{2}\left( {3\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{12} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$$- {\frac{\sin^{2}\left( {3\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{25.6} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$HRR₅$- {\frac{\sin^{2}\left( {5\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{20} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$$- {\frac{\sin^{2}\left( {5\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{42.7} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$HRR₇ ${- \frac{1}{7}}\bigwedge$$- {\frac{\sin^{2}\left( {7\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{59.7} \right)^{2} + \left( \frac{\sigma_{\phi}}{4\sqrt{2}} \right)^{2}} \right\rbrack}$HRR₉ ${- \frac{1}{9}}\bigwedge$$- {\frac{\sin^{2}\left( {9\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{76.8} \right)^{2} + \left( \frac{\sigma_{\phi}}{4\sqrt{2}} \right)^{2}} \right\rbrack}$HRR₁₁$- {\frac{\sin^{2}\left( {11\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{44} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$$- {\frac{\sin^{2}\left( {11\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{93.9} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$HRR₁₃$- {\frac{\sin^{2}\left( {13\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{52} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}$$- {\frac{\sin^{2}\left( {13\; {\pi d}} \right)}{\sin^{2}({\pi d})}\left\lbrack {\left( \frac{\sigma_{A}}{110.9} \right)^{2} + \left( \frac{\sigma_{\phi}}{4} \right)^{2}} \right\rbrack}${circumflex over ( )}Inherent decay value of the LO harmonic power

Gain Mismatch Reduction by Two-Stage 6P-HRM and 14P-HRM

The gain mismatch of two-stage 6P-HRM can be derived using a vectordiagram in FIG. 5( a). The three vectors in every circle have 45° phaseshifting for the 1^(st) harmonic. The vector magnitudes represent thegain ratio of the first stage, whereas the multiplying factors representthe gain ratios of the second stage. Also, the vectors of adjacentcircles have 45° phase shift. The relative error of the first and secondstages are denoted as α and β, respectively. Every corresponding vectorof the 3^(rd) harmonic has the same amplitude, but shifted by 3 times inphase. The two-stage approximated gain ratio of the 1^(st) harmonic canbe calculated as shown in FIG. 5( b). The total relative error of the3^(rd) harmonic is given by (the subscript 2-s implies a two-stage HRM),

$\begin{matrix}{{ɛ_{{2 - s},{{6P} - {HRM}}} = \frac{41 - {29\sqrt{2}} + {\left( {21 - {15\sqrt{2}}} \right)\alpha} + {\left( {21 - {14\sqrt{2}}} \right)\beta} + {21{\alpha\beta}}}{41 + {29\sqrt{2}} + {\left( {21 + {15\sqrt{2}}} \right)\alpha} + {\left( {21 + {14\sqrt{2}}} \right)\beta} + {21{\alpha\beta}}}},} & (1)\end{matrix}$

which can be approximated as −1.49×10⁻⁴−2.60×10⁻³α−1.46×10⁻²β+0.256αβ.This result is different from the derivation given in [9], since it uses1:42:1 as the gain ratio for both stages during the calculation, whichdoes not match the practical circuit. In our model the exact gain ratiosfor both stages are adopted. In our derivation, the 1^(st) term resultsfrom the approximation of the √2 by 41/29 and the 2^(nd) term appearsfrom the gain mismatch of the first stage; both are negligibly small.The 3^(rd) term is determined by the gain mismatch of the second stageand it is suppressed by 68.5 times. The 4^(th) term is even minor as itis the product of the first and second stage gain errors. Thus, the gainerror after two-stage approximation becomes insignificant.

A similar vector diagram for two-stage 14P-HRM can be drawn in FIG. 6(a). There are 7 vectors in every circle representing the 7 gain ratiosfor every single path. Every adjacent vector has 22.5° phase shifting.The two-stage approximated gain ratio of the 1st harmonic can becalculated as shown in FIG. 6( b). Under the same mismatch parameters as6P-HRM, the total relative error of the 3rd harmonic can be evaluated tobe,

$\begin{matrix}{{ɛ_{{2 - s},{{14P} - {HRM}}} = \frac{0.010 + {3.64\alpha} + {5.08 \times 10^{- 3}\beta} + {1.8{\alpha\beta}}}{27.17 + {6.23\alpha} + {7.84\beta} + {1.8{\alpha\beta}}}},} & (2)\end{matrix}$

which can be approximated as 3.78×10⁻⁴+0.134α+1.87×10⁻⁴β+6.62×10⁻²αβ. Itcan be observed that the gain mismatch of the first stage is suppressedby 7.46 times while the gain mismatch of the second stage is almostcancelled.Comparison with the Two-Stage HRM in Receiver [9]

As analyzed above, with the two-stage 6P-HRM and 14P-HRM, the gainmismatch becomes manageable. Recalling from FIG. 1, for a targeted HRRof 60 dB, the 6P-HRM (14P-HRM) should contribute just 36 dB (43 dB).Thus, the acceptable 3σ_(φ) is relaxed to 3.6° (1.6°) for the 8-phase(16-phase) LO as plotted in FIG. 7, where σ_(A)=1%. Both are muchrelaxed when compared with [9], which entails 0.03° LO phase error tobear the entire 60 dB HRR target. Thus, combining HRM with filtering ina TX should lead to significant power savings in the LO path. Moreover,as the HRR is mainly limited by the accuracy of the BB pre-gain ratios,the robustness of the two-stage HRM in TX should be better than that inreceiver [9] (its pre-gain ratio is at RF).

Implementations

FIG. 8( a) depicts the detailed schematic of the proposed TX accordingto a preferred embodiment of the present invention. The implementationis fully differential even it is exhibited as single-ended for brevity.The outputs of the upper and lower sub-band paths are combined at theDA, which should driver an off-chip power amplifier. The key buildingblocks are described below.

Co-Design of BB LPF, Mixer Banks and RF HRF

FIG. 8 (b) is one example of circuit diagram of lowpass filter (LPF) inFIG. 8 (a). The first-stage gain ratio is embedded into the BBpassive-RC LPF. Excellent matching over process variations is achievedvia using a ratio of resistors: R₂/(R_(I)+R₂). The −3-dB cutofffrequency f_(c) is given by,

$\begin{matrix}{{f_{C} = \frac{1}{2{\pi \left( R_{1}||R_{2} \right)}C_{1}}},} & (3)\end{matrix}$

For every path of the LPF, C₁ and R₁//R₂ are chosen to be 2 pF and 7.96kΩ, respectively, such that a fixed cutoff frequency of 10 MHz can beset, minimizing also the phase mismatch at the BB. FIG. 8 (c)illustrates one example of circuit diagram of mixer bank in FIG. 8 (a).The phase rotation and frequency up-conversion are realized using a bankof active mixers, with each unit. FIG. 8 (d) illustrates one example ofcircuit diagram of harmonic-rejection filter (HRF) in FIG. 8 (a). Sincethe 14P-HRM only rejects harmonics up to the 13^(th), the RF HRF isdesigned to suppress the 15^(th) harmonic by 36.5 dB to meet the 60 dBHRR target. It is a 2^(nd)-order passive-RC network featuring four (65,124, 235 and 456 MHz) and two (460 and 900 MHz) optimized cutoffsautomatically selected with the LO for the lower and upper sub-bands,respectively. The effect of process variations and mismatches on HRR isassessed by Monte-Carlo simulations. For instance, for a 65 MHz cutoff,the simulated standard deviation is 8.9 MHz. When transmitting a signalat 54 MHz (the toughest case), the corresponding HRR₃ (at 162 MHz)varies just ±1.3 dB, avoiding any calibration.A Wideband DA with an Embedded CLC-Ladder BSF

The schematic of the DA is depicted in FIG. 9( a). The segmented V-to-Iinput branches of the DA realize the required second-stage gain ratio.M₁ is source-degenerated by R_(d)C_(d) to improve the passband flatness.The effective transconductance g_(m,eff) is given by,

$\begin{matrix}{{g_{m,{eff}} = {\frac{g_{m\; 1}}{1 + {g_{m\; 1}R_{d}}}\frac{1 + {s\; 2R_{d}C_{d}}}{1 + {s\frac{2R_{d}C_{d}}{1 + {g_{m\; 1}R_{d}}}}}}},} & (4)\end{matrix}$

where g_(m1) is the transconductance of M₁, and R_(d) is theon-resistance of M_(d1) which also serves as a switch for changing thegain ratio at RF (4:5.6:4⇄4:3:4), where only the mid branch has to beswitchable. Although 5.6⇄3 is not integer-ratio switching, gain mismatchat the second stage is indeed minor.

The DA uses a thick-oxide MOSFET as the cascade device to allow using a2-V supply for better linearity. The combined output current is filteredin current mode by a 3rd-order passive-CLC BSF. The frequency responseof the BSF is given by,

$\begin{matrix}{{{H_{BSF}(s)} = \frac{1/g_{m\; 2}}{1 + {s\; 2\left( {C_{F\; 1} + C_{F\; 2}} \right)g_{m\; 2}} + {s^{2}2C_{F\; 1}L_{F}} + {s^{3}4C_{F\; 1}C_{F\; 2}{L_{F}/g_{m\; 2}}}}},} & (5)\end{matrix}$

where C_(F1)=C_(F2=2.37) pF and L_(F)=4.5 nH lead to a cutoff of 1.6GHz. After accounting the parasitic and package effects, the cutoff ofthe DA stays at 1.2 GHz. From Monte-Carlo simulations, the 1.2 GHzcutoff can have a standard deviation of 71.4 MHz. When transmitting asignal at 432 MHz (the toughest case), the corresponding HRR₃ at 1.296GHz varies just ±1.9 dB, which is acceptable without any calibration.The overall frequency response of the DA can be derived as,

$\begin{matrix}{{{H_{DA}(s)} = {\frac{v_{out}(s)}{v_{1}(s)} = \frac{g_{m\; 1}Z_{F}g_{m\; 2}R_{L}}{2\left( {1 + {g_{m\; 1}Z_{d}}} \right)\left( {1 + {s\; 2C_{F\; 1}Z_{F}} + {s^{2}2C_{F\; 1}L_{F}}} \right)}}},} & (6)\end{matrix}$

where g_(m2) is the transconductance of M₂, and Z_(d) is the impedanceof the RC degeneration as given by,

$\begin{matrix}{Z_{d} = {\frac{R_{d}}{1 + {s\; 2R_{d}C_{d}}}.}} & (7)\end{matrix}$

Together with the package model, the simulated frequency responses ofthe DA with and without the BSF and R_(d)C_(d)-degeneration are comparedin FIG. 9( b). It is clear that without the BSF the BW of the DA isexcessive (˜4 GHz), while the optimized response has small gain droopand shows a strong stopband rejection of around 65 dB/dec.

Wideband Low-LO_(ref) 8-/16-Phase LOG

Poly-phase LOGs are commonly based on dividers, necessitating ahigh-frequency reference LO to be supported by the frequencysynthesizer. As analyzed before, the required 3σ_(φ) of the 8-phase(16-phase) LO is relaxed to 3.6° (1.6°). Thus, the recently proposedinjection-locked 4-18-phase phase correctors (4PC/8PC) [11], [12] can beemployed to relax the frequency and tuning range of the reference LO.The 4PC [as shown in FIG. 10( a)] and 8PC [as shown in FIG. 10( b)] areinverter-only circuitry. They are expandable, by cascading more ofthemselves, to optimize the phase accuracy.

The inverters are classified into three sets and two types: set A is forinterpolating the intermediated phases. Set B is for natural-frequencysuppression which leads to a larger operating frequency range. Set C isfor signal injection and direct cascade of itself. For the two types,L-type stands for a larger device size than the S-type. The size ratiobetween L- and S-type inverters determines the locking range and thephase accuracy. A larger size ratio implies better phase-correctingability but a smaller locking range. The phase-correcting ability of 4PC(8PC) can also be enhanced by cascading more of themselves, at theexpense of power. In post-layout simulations for a 1.0° phase error, acascade of five 4PC with L/S=3 is minimum to progressively correct thephase error from 44°→14°→5.3°→1.9°→1.0° at 432 MHz with a total power of5.1 mW. Similarly, a cascade of six 8PC with L/S=3.75 is minimum tocorrect the phase error from 52°→11°→4.4°→2.1°→1.2°→1.0° at 432 MHz witha total power of 6.0 mW.

The proposed 8-116-phase LOG (FIG. 11) optimally combines differentphase correctors and even-ratio-only frequency dividers to cover theentire TV band, allowing a low-frequency LO_(ref) while offeringappropriate 8- and 16-phase LOs for different frequency segments, i.e.,54 to 108 MHz, 108 to 216 MHz, 216 to 432 MHz and 432 to 864 MHz. TheLO_(ref) is minimized to alleviate the design of a wideband synthesizer[13] when optimizing the power, VCO pulling and tuning agility (aconcern of CR for fast spectrum sensing). Moreover, the requireddivision ratios for generating the 16-phase LO from 54-4.32 MHz aresignificantly reduced. All dividers in the layout are connected in acoiled manner [14] to equalize the delays between LO paths. Thesimulated frequency ranges of the four segments are 35 to 131 MHz, 70 to263 MHz, 140 to 525 MHz and 280 to 1160 MHz. The overlaps givesufficient margins for PVT variations.

It will thus be seen that the invention provides design techniques andmeasurement results of a TV-band white-space TX. The TX combines thewideband and robustness features of two-stage 6P-/14P-HRM, with thepower and linearity benefits of passive-RC/-CLC filters, to manage theHRR fully on chip. Tested over 16 available 65 nm CMOS prototypes, theminimum HRR is 59.3 dB. The employed 8-/16-phase LOG is optimized viacombining injection-locked 4PC/8PC and even-ratio frequency dividers.The LOG not only lowers the LO-path power (2.5 to 14.2 mW), but also theentailed reference LO frequency (432 to 864 MHz) that has been a commonBW-bottleneck of most HRM-based architecture.

The improved performance of the present invention in comparison with theprior art is more apparent for its: (1) low required LO_(ref); (2)common BB inputs (differential and I/Q); (3) high power efficiency overthe TV band; and (4) high-and-robust HRR achieved fully on chip.

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the invention. The appearances of the phrase “in one embodiment” invarious places in the specification are not necessarily all referring tothe same embodiment.

The previous description of the disclosed exemplary embodiments isprovided to enable any person skilled in the art to make or use thepresent invention. Various modifications to these exemplary embodimentswill be readily apparent to those skilled in the art, and the genericprinciples defined herein may be applied to other embodiments withoutdeparting the spirit or scope of the invention. Thus, the presentinvention is not intended to be limited to the embodiments shown hereinbut is to be accorded the widest scope consistent with the principlesand novel features disclosed herein.

REFERENCES

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What is claimed is:
 1. A poly-phase local oscillator generator,comprising: a plurality of phase correctors configured to relaxfrequency and tuning range of a reference local oscillator (LO); and aplurality of frequency dividers coupled to the phase correctors, andconfigured to offer different frequency segments, wherein the pluralityof phase correctors are expandable by cascading more of the plurality ofphase correctors for enhancing phase-correcting ability.
 2. Thepoly-phase local oscillator generator of claim 1, wherein each of theplurality of phase correctors is an inverter-only circuitry containingonly inverters.
 3. The poly-phase local oscillator generator of claim 2,wherein the inverters included in the inverter-only circuitry of thephase correctors are classified into three sets: a first set used forinterpolating intermediated phases; a second set used fornatural-frequency suppression which leads to a larger operatingfrequency range; and a third set used for signal injection and directcascade of itself.
 4. The poly-phase local oscillator generator of claim2, wherein the inverters included in inverter-only circuitry of thephase correctors are classified into L-type and S-type inverters,wherein the L-type inverters have a larger device size than the S-typeinverters, and wherein a size ratio between the L-type and the S-typeinverters determines locking range and phase accuracy.
 5. The poly-phaselocal oscillator generator of claim 1, wherein the plurality of phasecorrectors are direct-injection-locked phase correctors.
 6. Thepoly-phase local oscillator generator of claim 1, wherein the pluralityof phase correctors are 4-phase phase correctors and 8-phase phasecorrectors.
 7. The poly-phase local oscillator generator of claim 1,wherein the plurality of frequency dividers are even-ratio-onlyfrequency dividers.